Robert Riordan /   System-Verilog

#System-Verilog

RISC-V CPU

Done
A RISC-V 32I CPU implemented in verilog and verified with pyuvm
#risc-v #pyuvm #system-verilog

FPGA based 8-Bit CPU

Done
An 8-bit CPU on a Tang Nano 9k FPGA
#fpga #system-verilog #pyuvm

       • © 2026  •  Robert Riordan

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