#Fpga

Configurable Logic Block

Work in progress

Converts any 4 inputs into 1 output

General Purpose Input Output

Work in progress

A general interface for the FPGA

Minimal FPGA

Work in progress

A custom FPGA built using 74-series logic

FPGA based 8-Bit CPU

An 8-bit CPU on a Tang Nano 9k FPGA

#fpga #system-verilog #pyuvm

Phase Lock Loop

Work in progress

A programmable clock

Interconnect

Work in progress

Programmable connections between modules

Demos

Example and explanation’s of 3 programs running

Verification with PyUVM

System verification using PyUVM

#fpga #uvm #pyuvm

Build System

An open source build system for the Tang Nano

#fpga #tangnano